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November 1990
Edition 5.0
DATA SHEET
SERIAL INPUT PLL FREQUENCY SYNTHESIZER
LOW POWER SERIAL INPUT PLL SYNTHESIZER WITH 1.1 GHz PRESCALER
The Fujitsu MB1502, utilizing BI-CMOS technology, is a single chip serial input PLL synthesizer with pulse-swallow function. The MB1502 contains a 1.1GHz two modulus prescaler that can select of either 64/65 or 128/129 divide ratio, control signal generator, 16-bit shift register, 15-bit latch, programmable reference divider (binary 14-bit programmable reference counter), 1-bit switch counter, phase comparator with phase conversion function, charge pump, crystal oscillator, 19-bit shift register, 18-bit latch, programmable divider (binary 7-bit swallow counter and binary 11-bit programmable counter) and analog switch to speed up lock up time.
It operates supply voltage of 5V typ. and achieves very low supply current of 8mA typ. realized through the use of Fujitsu Advanced Process Technology.
FEATURES
ï‚? High operating frequency: fIN MAX=1.1GHz (VIN MIN=10dBm)
ï‚? Pulse swallow function: 64/65 or 128/129
ï‚? Low supply current: ICC=8mA typ.
ï‚? Serial input 18-bit programmable divider consisting of:
�Binary 7-bit swallow counter: 0 to 127
�Binary 11-bit programmable counter: 16 to 2047
ï‚? Serial input 15-bit programmable reference divider consisting of:
�Binary 14-bit programmable reference counter: 8 to 16383
�1-bit switch counter (SW) sets divide ratio of prescaler
ï‚? On-chip analog switch achieves fast lock up time
ï‚? 2 types of phase detector output
�On-chip charge pump (Bipolar type)
�Output for external charge pum°p °
Plastic Package
DIP-16P-M04
Plastic Package
FPT-16P–M06
Pin Assignment
� Wide operating temperature: �0 C to +85 C
� 16-pin Plastic DIP Package (Suffix: —P)
16-pin Plastic Flat Package (Suffix: —PF)
ABSOLUTE MAXIMUM RATINGS (See NOTE)
RatIng Symbol Value Unit
VCC �.5 to +7.0 V
OSCIN OSCOUT VP
5 (TOP VIEW)
16 R
15 P
14 fOUT
13 BiSW
12 FC
Power Supply Voltage
VP VCC to 10.0 V
11 LE
Output Voltage VOUT �.5 to VCC +0.5 V Open-drain Voltage VOOP �.5 to 0.8 V
Output Current IOUT �10 m° A
10 Data
9 Clock
Storage Temperature TSTG �5 to +125 C
NOTE: Permanent device damage may occur if the above Absolute Maximum RatIngs are exceed- ed.Functional operation should be restricted to the condItions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
MB1502 Block Diagram
16-Bit Shift Register
16-Bit Shift Register
15-Bit Latch
15-Bit Latch
13 BiSW
Programmable
Reference Divider
Crystal
Binary 14-Bit
Comparator
OSCIN 1
OSCOUT 2
Oscillator
Circuit
Reference Counter SW
Prescaler
Circuit
19-Bit Shift Register
19-Bit Shift Register
18-Bit Latch
7-Bit Latch 11-Bit Latch
14 fOUT
Programmable Divider
Data 10
Clock 9
Control
1-Bit Latch
Binary 7-Bit
Swallow Counter
Binary 11-Bit
Programmable Counter
Control Circuit
PIN DESCRIPTION
Name I/O Description
1 OSCIN
2 OSCOUT
I Oscillator input.
O Oscillator output.
A crystal is placed between OSCIN and OSCOUT.
3 VP �Power supply input for charge pump and analog switch.
4 VCC �Power supply voltage input.
5 D O Charge pump output.
The characteristics of charge pump is reversed depending upon FC input.
6 GND �Ground
Phase comparator output.
Normally this pin outputs high level. While the phase difference of fr, and fp exists, this pin outputs low level.
8 f l Prescaler input.
The connection with an external VCO should be AC connection.
9 Clock I Clock input for 19-bit shift register and 16-bit shift register.
On rising edge of the clock shifts one bit of data into the shift registers.
Binary serial data input.
10 Data l
11 LE I
12 FC l
13 BISW O
14 fOUT O
The last bit of the data is a control bit which specified destination of shift registers.
When this bit is high level and LE is high level, the data stored in shift register is transferred to 15-bit latch. When this bit is low level and LE is high level, the data is transferred to 18-bit latch.
Load enable input (with internal pull up resistor).
When LE is high or open, the data stored in shift register is transferred into latch depending upon the control bit. At the time, internal charge pump output to be connected to BISW pin because internal analog switch
becomes ON state.
Phase select input of phase comparator (with internal pull up resistor).
When FC is low level, the characteristics of charge pump, phase comparator is reversed. FC input signal is also used to control fOUT pin (test pin) output level for fr or fp.
Analog switch output.
Usually BISW pin is set high-impedance state. When internal analog switch is ON (LE pin is high level), this pin outputs internal charge pump state.
Monitor pin of phase comparator input.
fOUT pin outputs either programmable reference divider output (fr) or programmable divider output (fp)
depending upon FC pin input level.
O Outputs for external charge pump.
O The characteristics are reversed according to FC input.
P pin is N-channel open drain output.
FUNCTIONAL DESCRIPTIONS
SERIAL DATA INPUT
Serial data input is achieved by three inputs, such as Data pin, Clock pin and LE pin. Serial data input controls 15-bit programmable reference divider and 18-bit programmable divider, respectively.
Binary serial data is input to Data pin.
On rising edge of clock shifts one bit of serial data into the internal shift registers and when load enable pin is high level or open, stored data is transferred into latch depending upon the control bit.
Control data “H�data is transferred into 15-bit latch. Control data “L�data is transferred into 18-bit latch.
PROGRAMMABLE REFERENCE DIVIDER
Programmable reference divider consists of 16-bit shift register, 15-bit latch and 14-bit reference counter. Serial 16-bit data format is shown below.
Control bit Divide ratio of prescaler setting bit
LSB MSB
C S S S S
1 2 3 4
S S S S
5 6 7 8
9 10 11
S S S S
12 13 14 W
Divide ratio of programmable reference counter setting bit
14-BIT PROGRAMMABLE REFERENCE COUNTER DIVIDE RATIO
Divide Ratio R
S S S S S S
14 13 12 11 10 9
S S S S S S S S
8 7 6 5 4 3 2 1
8 0 0 0 0 0 0 0 0 0 0 1 0 0 0
9 0 0 0 0 0 0 0 0 0 0 1 0 0 1
ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?16383 1 1 1 1 1 1 1 1 1 1 1 1 1 1
NOTES: Divide ratio less than 8 is prohibited.
Divide ratio: 8 to 16383
SW: This bit selects divide ratio of prescaler. SW=H : 64
SW=L :128
S1 to S14: These bits select divide ratio of programmable reference divider.
C: Control bit (sets as high level).
Data is input from MSB side.
PROGRAMMABLE DIVIDER
Programmable divider consists of 19-bit shift register, 18-bit latch, 7-bit swallow counter and 11-bit programmable counter.
Serial 19-bit data format is shown on following page.
Control bit
LSB MSB
S S S S
3 4 5 6
S S S S
1 1 1 1
0 1 2 3
S S S S S
1 1 1 1 1
4 5 6 7 8
Divide ratio of swallow counter setting bit
Divide ratio of programmable counter setting bit
7-BIT SWALLOW COUNTER DIVIDE RATIO
Divide Ratio A
S S S S
7 6 5 4
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 1
ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?127 1 1 1 1 1 1 1
NOTE: Divide ratio: 0 to 127
11-BIT PROGRAMMABLE COUNTER DIVIDE RATIO
Divide Ratio N
S S S S
1 1 1 1
8 7 6 5
S S S S
1 1 1 1
4 3 2 1
16 0 0 0 0 0 0 1 0 0 0 1
17 0 0 0 0 0 0 1 0 0 0 1
ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?ï‚?2047 1 1 1 1 1 1 1 1 1 1 1
NOTES: Divide ratio less than 16 is prohibited.
Divide ratio: 16 to 2047
S1 to S7: Swallow counter divide ratio setting bit. (0 to 127)
S8 to S18: Programmable counter divide ratio setting bit. (16 to 2047)
C: Control bit (sets as low level).
Data is input from MSB side.
PULSE SWALLOW FUNCTION
fvco = [(PxN)+A] x fosc ï‚?R
fVCO: Output frequency of external voltage controlled oscillator (VCO)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0ï‚£Aï‚?27, A<N)
fOSC: Output frequency of the external reference frequency oscillator
R: Preset divide ratio of binary 14-bit programmable reference counter (8 to 16383)
P: Preset modulus of external dual modulus prescaler (64 or 128)
Serial Data Input Timing
S18=MSB
S17 S10 S9 S1=LSB
(C: Control bit)
*(SW) (S14) (S (S7) (S1) (C: Control bit)
t1 t2 t3
t1 �t5 �1 s t4
NOTES: Parenthesis data is used for setting divide ratio of programmable reference divider.
On rising edge of clock shifts one bit of data in the shift register.
PHASE CHARACTERISTICS
FC pin is provided to change phase characteristics of phase comparator. Characteristics of internal charge pump output level (Do), phase comparator output level (R, P) are reversed depending upon FC pin input level. Also, monitor pin (fOUT) output level of phase comparator is controlled by FC pin input level. The relation between outputs (DO, R, P) and FC input level are shown below.
FC=H or open FC=L
DO R P
DO R P
fr > fp H L L (fr) L H Z (fp) fr < fp L H Z (fr) H L L (fp) fr = fp Z L Z (fr) Z L Z (fp)
Note: Z = (High impedance)
VCO CHARACTERISTICS
1 Depending upon VCO characteristics,
FC pin should be set accordingly:
�When VCO characteristics are like1,
FC should be set High or open circuit;
�When VCO characteristics are like 2, FC should be set Low.
VCO INPUT VOLTAGE
NOTES: Phase difference detection range: � to +2
Spike appearance depends on charge pump characteristics. Also, the spike is output in order to diminish dead band.
When fr > fp or fr < fp, spike might not appear depending upon charge pump characteristics.
ANALOG SWITCH
ON/OFF of analog switch is controlled by LE input signal. When the analog switch is ON, internal charge pump output (DO) to be connected to BlSW pin. When the analog switch is OFF, BlSW pin is set to high-impedance state.
LE=H (Changing the divide ratio of internal prescaler) : Analog switch=ON LE=L (Normal operating mode): Analog switch=OFF
LPF time constant is decreased in order to insert a analog switch between LPF1 and LPF2 when channel of PLL is changing. Thus, lock up time is decreased, that is, fast lock up time is achieved.
CHARGE PUMP LPF-1 LPF-2 VCO
ANALOG SW
(CONTROL SIGNAL)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol
Min Typ Max
Power Supply Voltage
VCC 4.5 5.0 5.5 V VP VCC VP 8.0 V
Input Voltage VI GND VCC °V Operating Temperature TA �0 85 C
ELECTRICAL CHARACTERISTICS
(Vcc=4.5 to 5.5V, TA=�0 to +85oC, unless otherwise noted.)
Parameter Symbol Condition
Min Typ Max
Power Supply Current ICC Note 1 8.0 12.0 mA
fin fin Note2 10 1100 MHz
Operating Frequency
Input Sensitivity
OSCIN fOSC 12 20 MHz fin Vfin �0 6 dBm
OSCIN VOSC 0.5 VPP
High-level Input Voltage Except fin
VIH VCCx0.7 V
Low-level Input Voltage
and OSCIN VIL VCCx0.3 V
High-level Input Current Data IIH 1.0 A Low-level Input Current Clock IIL �.0 A OSCIN IOSC �0 A
Input Current
LE, FC ILE �0 A
High-level Output Current Except DO VOH VCC = 5 V 4.4 V
Low-level Output Current
N-channel Open Drain Cutoff
OSCOUT VOL 0.4 V
VP = VCC to 8V
Current DO, P IOFF
VOOP= GND to 8V 1.1 A
Except DO IOH �.0 mA Output Current and
OSCOUT IOL 1.0 mA
Analog Switch On Resistor RON 25 Q
NOTE: 1: f in = 1.1GHz, OSClN=12MHz, Vcc=5V. Inputs are grounded and outputs are open.
2: AC coupling. Minimum operating frequency is measured when a capacitor 1000pF is connected.
TYPICAL CHARACTERISTICS CURVES
INPUT SENSITIVITY CHARACTERISTICS
INPUT IMPEDANCE CHARACTERISTICS
TYPICAL APPLICATION EXAMPLE
VPX(6V)
LPF VCO
Charge Pump Selection
(Internal or external)
FROM CONTROLLER
fp fr
FC LE Data Clock 47k 47k
16 15 14 13 12 11 10 9
1 2 3 4 5 6 7 8
OSCIN OSCOUT VP VCC DO
X’tal 1000pF
VCC (5V)
LOCK DET
0.01 F
Vp, Vpx : 8V max
C1, C2 : Depends on crystal oscillator
LE, FC : With internal pull up resistor
P : Open drain output
PACKAGE DIMENSIONS
16–Lead Plastic Dual In–Line Package
(Case No.: DIP�6P–M04)
.770 +.008
15ï‚°MAX
�012 (19.55 �.30 )
INDEX-1
.244ï‚?010 (6.20ï‚?.25)
.300(7.62) TYP
INDEX-2
.039 +.012
(0.99 +0.30 )
.060 +.012
(1.52 +0.30)
.010ï‚?002 (0.25ï‚?.05)
.172(4.36)MAX
.118(3.00)MIN
.050(1.27) MAX
.100(2.54) TYP
.018ï‚?003 (0.46ï‚?.0
.020(0.51)MIN
Dimensions in
�991 FUJITSU LIMITED D16033S-2C
inches (millimeters)
.400 +.010
16–Lead Plastic Flat Package
(Case No.: FPT�6P–M06)
.089(2.25)MAX (MOUNTING HEIGHT)
(10.15 )
.002(0.05)MIN (STAND OFF HEIGHT)
.307ï‚?016 (7.80ï‚?.40)
.268 +.016
.209ï‚?012 (5.30ï‚?.30)
�008 (6.80 �.20 )
.020ï‚?008 (0.50ï‚?.20)
.050(1.27)
.018ï‚?004
(0.45�.10) �005(0.13) M
.006 �001 (0.15�.02 )
Details of “A�part
.016(0.40)
Details of “B�part
.006(0.15)
.004(0.10)
.350(8.89) REF
.008(0.20)
.007(0.1 MAX
.027(0.6 MAX
.008(0.20)
.007(0.1 MAX
.027(0.6 MAX
�991 FUJITSU LIMITED F16015S-2C
Dimensions in inches (millimeters)
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�1990 FUJITSU LIMITED JV0123-90YA3
Printed in Japan